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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/304

Title: Soft secondary electron programming for floating gate NOR flash EEPROMs
Authors: BHARATH KUMAR, P
NAIR, DR
MAHAPATRA, S
Keywords: flash memories
hot carriers
logic gates
Issue Date: 2005
Publisher: IEEE
Citation: Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 27 June-1 July 2005, 146-149
Abstract: A novel scheme called soft secondary electron programming (SSEP) is introduced and shown to be a promising programming mechanism for scaled NOR flash EEPROMs. SSEP involves use of an "optimum" VB that results in a lower drain disturb compared to both channel hot electron (CHE) and channel initiated secondary electron (CHISEL) mechanisms. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, and better program/disturb margin compared to CHISEL at similar program speed or disturb time.
URI: 10.1109/IPFA.2005.1469149
http://hdl.handle.net/10054/304
http://dspace.library.iitb.ac.in/xmlui/handle/10054/304
ISBN: 0-7803-9301-5
Appears in Collections:Proceedings papers

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