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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/295

Title: Device optimization of bulk FinFETs and its comparison with SOI FinFETs
Authors: MANOJ, CR
MEENAKSHI, N
DHANYA, V
RAMGOPAL RAO, V
Keywords: cmos integrated circuit
mosfet
leakage currents
silicon-on-insulator
Issue Date: 2007
Publisher: IEEE
Citation: Proceedings of the International Workshop on Physics of Semiconductor Devices, Mumbai, India, 16-20 December 2007, 134-137
Abstract: FinFETs are the leading candidates for sub 32nm technology node owing to their increased immunity to short channel effects and better scalability. Most of the fabricated FinFETs are on SOI substrates. But fabrication of FinFETs using the bulk CMOS substrates instead of SOI technology is also of interest since it reduces the process costs. But bulk FinFETs have the disadvantage of sub channel leakage for very short channel lengths. Reported work on Bulk FinFETs, use highly doped channel for preventing the leakage. Body doping just beneath the fin is also considered a possible way to prevent this leakage. In this work, we evaluate the effect of different body doping profiles in un-doped channel bulk FinFETs, for controlling the sub channel leakage and propose the optimization of the same. We also bring out the other advantages of body doping such as an increased immunity to body effect from the circuit performance point of view. We also show that device parasitics play a crucial role in the optimization of nano scale bulk FinFETs.
URI: 10.1109/IWPSD.2007.4472472
http://hdl.handle.net/10054/295
http://dspace.library.iitb.ac.in/xmlui/handle/10054/295
ISBN: 978-1-4244-1728-5
Appears in Collections:Proceedings papers

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