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|Title:||The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs|
RAMGOPAL RAO, V
Integrated Circuit Reliability
|Citation:||Proceedings of the 33rd Conference on European Solid-State Device Research, Estoril, Portugal, 16-18 September 2003, 541-544|
|Abstract:||The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.|
|Appears in Collections:||Proceedings papers|
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