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|Title:||The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs|
Integrated Circuit Testing
Integrated Memory Circuits
|Citation:||Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 7-11 July 2003, 164-167|
|Abstract:||In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (Lfg). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (Vcg) and Vd. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (Tp). However the margin becomes identical when compared after 100K P/E cycling.|
|Appears in Collections:||Proceedings papers|
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