Please use this identifier to cite or link to this item:
|Title:||Substrate bias effect on cycling induced performance degradation of flash EEPROMs|
Integrated Circuit Reliability
Integrated Memory Circuits
|Citation:||Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 223-226|
|Abstract:||Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for VB<0 operation under identical interface damage as the VB=0 case. As a consequence, programming under VB<0 condition has been found to cause lower degradation of programming time and programmed VT due to cycling.|
|Appears in Collections:||Proceedings papers|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.