Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/10054/288
Title: Substrate bias effect on cycling induced performance degradation of flash EEPROMs
Authors: MAHAPATRA, S
SHUKURI, S
BUDE, JD
Keywords: Pld Programming
Flash Memories
Integrated Circuit Reliability
Integrated Memory Circuits
Substrates
Issue Date: 2003
Publisher: IEEE
Citation: Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 223-226
Abstract: Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for VB<0 operation under identical interface damage as the VB=0 case. As a consequence, programming under VB<0 condition has been found to cause lower degradation of programming time and programmed VT due to cycling.
URI: 10.1109/ICVD.2003.1183140
http://hdl.handle.net/10054/288
http://dspace.library.iitb.ac.in/xmlui/handle/10054/288
ISBN: 0-7695-1868-0
Appears in Collections:Proceedings papers

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