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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/226

Title: Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering
Authors: SHRIVASTAV, G
MAHAPATRA, S
RAMGOPAL RAO, V
VASI, J
Keywords: mosfet
optimisation
semiconductor device models
Issue Date: 2001
Publisher: IEEE
Citation: Proceedings of the Fourteenth International Conference on VLSI Design, Bangalore, India, 3-7 January 2001, 475-478
Abstract: A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D2FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.
URI: 10.1109/ICVD.2001.902703
http://hdl.handle.net/10054/226
http://dspace.library.iitb.ac.in/xmlui/handle/10054/226
ISBN: 0-7695-0831-6
Appears in Collections:Proceedings papers

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