Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/10054/200
Title: Border-trap characterization in high-κ strained-Si MOSFETs
Authors: MAJI, DEBABRATA
DUTTAGUPTA, SP
RAMGOPAL RAO, V
YEO, CHIA CHING
CHO, BYUNG-JIN
Keywords: Drain Current
Gate Dielectrics
Hysteresis
Semiconducting Silicon
Issue Date: 2007
Publisher: IEEE
Citation: IEEE Electron Device Letters 28(8), 731-33
Abstract: In this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si0.8Ge0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
URI: http://dx.doi.org/10.1109/LED.2007.902086
http://hdl.handle.net/10054/200
http://dspace.library.iitb.ac.in/xmlui/handle/10054/200
ISSN: 0741-3106
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