Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/10054/185
Title: SEU reliability analysis of advanced deep-submicron transistors
Authors: VASI, J
JAIN, PALKESH
LAL, RAKESH
Keywords: Computer Simulation
Dielectric Materials
Interfaces (Materials)
Reliability
Issue Date: 2005
Publisher: IEEE
Citation: IEEE Transactions on Device and Materials Reliability 5 (2), 289-95
Abstract: A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-κ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-κ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.
URI: http://dx.doi.org/10.1109/TDMR.2005.848325
http://hdl.handle.net/10054/185
http://dspace.library.iitb.ac.in/xmlui/handle/10054/185
ISSN: 1530-4388
Appears in Collections:Article

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