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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/1617

Title: Automated synthesis of assertion monitors using visual specifications
Authors: GADKARI, A
RAMESH, S
Keywords: network protocols
time domain analysis
graphical user interfaces
computer hardware
Issue Date: 2005
Publisher: IEEE Computer Society
Citation: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 7-11 March 2005, 390-395
Abstract: Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple clock domains. It has well-defined graphical and textual syntax and formal semantics based on synchronous language paradigm enabling formal analysis of specifications. In this paper we provide an overview of CESC language with few illustrative examples. The algorithm for automated synthesis of assertion monitors from CESC specifications is described. A few examples from standard bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of monitor synthesis algorithm.
URI: 10.1109/DATE.2005.74
http://hdl.handle.net/10054/1617
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1617
ISBN: 0769522882
Appears in Collections:Proceedings papers

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