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| Title: | Reasoning about digital systems using temporal logic |
| Authors: | BAPAT, S
VENKATESH, G |
| Keywords: | cad
formal logic
temporal logic
digital system |
| Issue Date: | 1986 |
| Publisher: | IEEE Computer Society |
| Citation: | Proceedings of the 23rd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, 29 June-2 July 1986, 215-219 |
| Abstract: | Temporal logic is proposed as a medium to describe the timing behaviour of digital systems. Queries on the timing properties of the digital systems can then be answered by testing the satisfiability of appropriately constructed temporal formulae. We suggest ways of improving the standard tableau method of testing the satisfiability of these formulae, and discuss results obtained from an implementation of this method. We claim that this can serve as a designers assistant to debug designs. |
| URI: | 10.1145/318013.318047
http://hdl.handle.net/10054/1603
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1603 |
| ISBN: | 0-8186-0702-5 |
| Appears in Collections: | Proceedings papers
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