DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Article >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/148

Title: Optimization and realization of sub-100-nm channel length single halo p-MOSFETs
Authors: RAMGOPAL RAO, V
BORSE, DG
MANJULA RANI, KN
JHA, NEERAJ K
CHANDORKAR, AN
VASI, J
CHENG, B
WOO, JCS
Keywords: mosfet
hot carriers
ion implantation
semiconductor device reliability
semiconductor doping
Issue Date: 2002
Publisher: IEEE
Citation: IEEE Transactions on Electron Devices 49(6), 1077-79
Abstract: Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle VT adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes.
URI: http://dx.doi.org/10.1109/TED.2002.1003752
http://hdl.handle.net/10054/148
http://dspace.library.iitb.ac.in/xmlui/handle/10054/148
ISSN: 0018-9383
Appears in Collections:Article

Files in This Item:

File Description SizeFormat
2166885.61 kBUnknownView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback