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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/144

Title: Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs
Authors: PATIL, MB
VINAY KUMAR, D
NARASIMHULU, K
REDDY, PS
BAGHINI, MS
SHARMA, DK
RAMGOPAL RAO, V
Keywords: cmos analogue integrated circuit
mosfet
analogue integrated circuit
circuit simulation
integrated circuit layout
table lookup
Issue Date: 2005
Publisher: IEEE
Citation: IEEE Transactions on Electron Devices 52(7), 1603-09
Abstract: Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-/spl mu/m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device.
URI: http://dx.doi.org/10.1109/TED.2005.850941
http://hdl.handle.net/10054/144
http://dspace.library.iitb.ac.in/xmlui/handle/10054/144
ISSN: 0018-9383
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