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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/10735

Title: Drain current model for nanoscale double-gate MOSFETs
Authors: HARIHARAN, V
THAKKER, R
SINGH, K
SACHID, AB
PATIL, MB
VASI, J
RAO, VR
Keywords: threshold voltage model
soi mosfets
dg mosfets
simulation
si
Issue Date: 2009
Publisher: PERGAMON-ELSEVIER SCIENCE LTD
Citation: SOLID-STATE ELECTRONICS, 53(9), 1001-1008
Abstract: A closed form inversion charge-based drain current model for a short channel symmetrically driven, lightly doped symmetric double-gate MOSFET (SDGFET) is presented. The model has physical origins, but has some fitting parameters included in order to yield a better match with TCAD device simulations. Velocity saturation and channel length modulation effects are self-consistently included in the model. The incorporation of DIBL effects in the model is based on a solution of the two-dimensional Laplace equation that had been reported earlier and that is believed to be especially suited when the physical gate-oxide thickness is not negligible compared to the silicon body thickness. Addition of support for body doping and low-field mobility degradation is also presented. A very good match is shown in I(d)-V(g), I(d)-V(d) and g(DS)-V(d) curves and a reasonable match is shown in g(m)-V(g) curves, when compared with 2D device simulations. The match in various characteristics is shown for devices as short as 20 nm. (C) 2009
URI: http://dx.doi.org/10.1016/j.sse.2009.05.008
http://dspace.library.iitb.ac.in/xmlui/handle/10054/10735
http://hdl.handle.net/10054/10735
ISSN: 0038-1101
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