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|Title: ||Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes|
|Authors: ||HARISH, BP|
|Issue Date: ||2006|
|Publisher: ||PERGAMON-ELSEVIER SCIENCE LTD|
|Citation: ||SOLID-STATE ELECTRONICS, 50(7-8), 1252-1260|
|Abstract: ||A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I-on at the device level, and the variation in rising/failing edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit x 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current Ion, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level. (c) 2006|
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