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|Title:||Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation|
Integrated Circuit Design
Integrated Memory Circuits
|Citation:||IEEE Transactions on Device and Materials Reliability 4(1), 32-37|
|Abstract:||Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated program/erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower program/disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.|
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