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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2930

Title: 6-bit low-power subranging-ADC with increased throughput
Authors: GOWDHAMAN, SK
BAGHINI, MS
Issue Date: 2010
Publisher: IEEE
Citation: 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,497-500
Abstract: This paper describes a high-speed low-power subranging Flash ADC designed in 90nm Mixed-Mode CMOS process. The maximum speed of subranging-ADC is limited by the time taken for the fine-ADC reference to settle. The proposed method splits optimally the total time taken for the coarse-ADC and fine-ADC comparisons to achieve the maximum possible clock speed. An auxiliary track-and-hold has been used in the interleaved track-and-hold to introduce 1/2 clock-cycle delay. Simulations results show that the subranging-ADC achieves SFDR of 37.7 dB at sampling rate of 1.54GS/s for 360MHz input and dissipates 15 mW power from I-V supply. It has 4.6 ENOB @ Nyquist and FoM of 0.4 pJ/conv. step. Minimum-size devices have been used in the comparator to achieve low-power. A digital offset calibration method has been used to reduce the offset of comparators.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/16454
http://hdl.handle.net/100/2930
ISBN: 978-1-4244-7773-9
ISSN: 1548-3746
Appears in Collections:Proceedings papers

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