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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2661

Title: Synchronous protocol automata : a framework for. modelling and verification of SoC communication architectures
Authors: D'SILVA, V
RAMESH, S
SOWMYA, A
Issue Date: 2004
Publisher: IEEE COMPUTER SOC
Citation: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS,390-395
Abstract: Plug-n-Play style Intellectual Property(IP) reuse in System on Chip(SoC) design is facilitated by the use of an on-chip bus architecture. We present a synchronous, Finite State Machine based framework for modelling communication aspects of such architectures. This formalism has been developed via interaction with designers and the industry and is intuitive and lightweight. We have developed cycle accurate methods to formally specify protocol compatibility and component composition and show how our model can be used for compatibility verification, interface synthesis and model checking with automated specification. We demonstrate the utility of our framework by modelling the AMBA bus architecture including details such as pipelined operation, burst and split transfers, the AHB-APB bridge and arbitration features.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/16071
http://hdl.handle.net/100/2661
ISBN: 0-7695-2085-5
Appears in Collections:Proceedings papers

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