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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2440

Title: Highly robust nanoscale planar double-Gate MOSFET Device and SRAM cell immune to Gate-misalignment and process variations
Authors: SACHID, AB
KULKARNI, GS
BAGHINI, MS
SHARMA, DK
RAO, VR
Issue Date: 2009
Publisher: IEEE
Citation: 2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY,13-16
Abstract: Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved. A standard 6T-SRAM cell designed using the optimized devices shows better read and hold static noise margins, and lower variations in SNM and leakage power compared to a conventional DG-MOSFET.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15778
http://hdl.handle.net/100/2440
ISBN: 978-1-4244-3831-0
Appears in Collections:Proceedings papers

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