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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2324

Title: Parasitics effects in multi gate MOSFETs
Authors: MANOJ, CR
MANGAL, A
RAO, VR
TSUTSUI, K
IWAI, H
Issue Date: 2006
Publisher: IEEE
Citation: 2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS,255-260
Abstract: The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K similar to 15, similar to hafnium oxide) is integrated in a multi-gate transistor a 5X increase (compared to the SiO(2)) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.
URI: http://dx.doi.org/10.1109/IWNC.2006.4570996
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15558
http://hdl.handle.net/100/2324
ISBN: 978-1-4244-0603-6
Appears in Collections:Proceedings papers

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