Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation : understanding the anomalous breakdown and optimization of P/E conditions

Abstract

Large memory window (6-9V) program/erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant voltage stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence, and energy on the defect generation process in the gate stack. Degradation during P and E are isolated to allow individual optimization for improving the cycling reliability. P/E cycling endurance >10(4) at 8V MW and >2.5x10(3) at 9V MW are shown for first time in metal NC memory devices using the proposed distributed cycling scheme.