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|Title: ||Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generation|
|Authors: ||SINGH, PK|
|Keywords: ||nonvolatile memory applications|
|Issue Date: ||2009|
|Citation: ||2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2,301-306|
|Abstract: ||Nanocrystal (NC) based memory devices are considered a possible alternative for floating gate (FG) replacement below 30nm node. In this work, endurance reliability of Pt NC devices is investigated for single layer (SL) and dual layer (DL) structures. The degradation in the devices due to Program/Erase (P/E) stress is investigated. Relative improvement in reliability of DL structure over SL structure is shown. A physical model for defect generation in the gate stack is proposed which is able to explain endurance and post-cycling characteristics. Dual layer structure is shown to have better inherent reliability over single layer structure.|
|Appears in Collections:||Proceedings papers|
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