DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2303

Title: Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generation
Authors: SINGH, PK
BISHT, G
SIVATHEJA, M
SANDHYA, C
MUKHOPADHYAY, G
MAHAPATRA, S
HOFMANN, R
SINGH, K
KRISHNA, N
Keywords: nonvolatile memory applications
performance
fabrication
Issue Date: 2009
Publisher: IEEE
Citation: 2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2,301-306
Abstract: Nanocrystal (NC) based memory devices are considered a possible alternative for floating gate (FG) replacement below 30nm node. In this work, endurance reliability of Pt NC devices is investigated for single layer (SL) and dual layer (DL) structures. The degradation in the devices due to Program/Erase (P/E) stress is investigated. Relative improvement in reliability of DL structure over SL structure is shown. A physical model for defect generation in the gate stack is proposed which is able to explain endurance and post-cycling characteristics. Dual layer structure is shown to have better inherent reliability over single layer structure.
URI: http://dx.doi.org/10.1109/IRPS.2009.5173268
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15531
http://hdl.handle.net/100/2303
ISBN: 978-1-4244-2888-5
Appears in Collections:Proceedings papers

Files in This Item:

File Description SizeFormat
Reliability of single and dual layer .pdf532.24 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback