An ultra low-energy DAC for successive approximation ADCs

Abstract

An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis shows that energy dissipation per bit can be reduced to the minimum possible normalized level, which is approximately 200 times lower than reported theoretical values. Simulation results of the proposed DAC in 90nm UMC MM CMOS process are also presented.