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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2267

Title: An ultra low-energy DAC for successive approximation ADCs
Authors: GOPAL, HV
BAGHINI, MS
Issue Date: 2010
Publisher: IEEE
Citation: 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS,3349-3352
Abstract: An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis shows that energy dissipation per bit can be reduced to the minimum possible normalized level, which is approximately 200 times lower than reported theoretical values. Simulation results of the proposed DAC in 90nm UMC MM CMOS process are also presented.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15665
http://hdl.handle.net/100/2267
ISBN: 978-1-4244-5309-2
ISSN: 0271-4302
Appears in Collections:Proceedings papers

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