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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2231

Title: To influence of process variations on the halo MOSFETs and its implications on the analog circuit performance
Authors: NARASIMHULU, K
NARENDRA, SG
RAO, VR
Keywords: asymmetric channel profile
cmos technology
design
Issue Date: 2004
Publisher: IEEE COMPUTER SOC
Citation: 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA,545-550
Abstract: Lateral Asymmetric Channel (LAC) and Double Halo (DH) MOSFETs have been reported to exhibit excellent properties for mixed signal CMOS applications. In this work, the effect of process variations such as gate oxide thickness, implantation parameters, and channel length are systematically investigated on the device and analog circuit performance for all these technologies. The performance parameters of LAC and DH differential amplifiers and current mirror circuits are evaluated, using mixed-mode simulations, as a function of process induced mismatch. Our simulation results on differential amplifiers and current mirrors show that, an identical V, mismatch in CON, DH, and LAC devices results in a lower variation in the circuit parameters for LAC technologies. It is found that, for a specified circuit parameter variation, almost a 25% higher V, mismatch is tolerable with LAC technologies as compared to the CON technologies.
URI: http://dx.doi.org/10.1109/ICVD.2004.1260976
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15485
http://hdl.handle.net/100/2231
ISBN: 0-7695-2072-3
Appears in Collections:Proceedings papers

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