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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2176

Title: FPGA implementation of a single-precision floating-point multiply-accumulator with single-cycle accumulation
Authors: PAIDIMARRI, A
CEVRERO, A
BRISK, P
IENNE, P
Issue Date: 2009
Publisher: IEEE COMPUTER SOC
Citation: PROCEEDINGS OF THE 2009 17TH IEEE SYMPOSIUM ON FIELD PROGRAMMABLE CUSTOM COMPUTING MACHINES,267-270
Abstract: This paper describes an FPGA implementation of a single-precision floating-point multiply-accumulator (FPMAC) that supports single-cycle accumulation while maintaining high clock frequencies. A non-traditional internal representation reduces the cost of mantissa alignment within the accumulator. The FPMAC is evaluated on an Altera Stratix III FPGA.
URI: http://dx.doi.org/10.1109/FCCM.2009.50
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15417
http://hdl.handle.net/100/2176
ISBN: 978-0-7695-3716-0
Appears in Collections:Proceedings papers

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