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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2076

Title: Bottleneck identification techniques leading to simplified performance models for efficient design space exploration in VLSI memory systems
Authors: HAZARI, G
DESAI, MP
SRINIVAS, G
Keywords: architectures
technology
Issue Date: 2010
Publisher: IEEE COMPUTER SOC
Citation: 23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN,15-20
Abstract: High performance VLSI systems are being built as multiprocessor systems-on-chip The number of processors and their performance is rising rapidly while the change is slower for the memories The memory system is often a performance bottleneck in terms of either its bandwidth or latency We propose sensitivity analysis as a means to pinpoint the bottleneck We Introduce a novel randomized technique to measure the sensitivities within cycle accurate simulators The sensitivity measures identify the bottleneck regions of the design space, within which simplified performance models can be used for optimization We demonstrate this methodology on the Augmint-MemSim simulator, which is a cycle accurate model for multi-processor systems with a distributed memory sub-system We empirically show that (i) Performance predictions from simplified models are strongly correlated with the simulator in the high sensitivity regions (u) The simplified models speed up design space exploration by 2 - 3 orders of magnitude over the simulator resulting in better design solutions
URI: http://dx.doi.org/10.1109/VLSI.Design.2010.45
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15607
http://hdl.handle.net/100/2076
ISBN: 978-1-4244-5541-6
Appears in Collections:Proceedings papers

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