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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2074

Title: Exploiting hybrid analysis in solving electrical networks
Authors: SANKAR, VS
NARAYANAN, H
PATKAR, SB
Issue Date: 2009
Publisher: IEEE COMPUTER SOC
Citation: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS,206-211
Abstract: In this paper we use topological hybrid analysis (mixture of nodal analysis and loop analysis) to solve circuits with resistors, voltage sources, current sources and diodes with exponential characteristics. In topological hybrid analysis [3], from the given network two smaller circuits are derived and solved simultaneously satisfying certain boundary conditions and this results in a solution of the original network. Our main emphasis is on non planar circuits with a large conductance range. The reason for this is that for non planar circuits preconditioned Conjugate Gradient method seems to perforin very well but its convergence will be adversely affected once the ratio of maximum to minimum. conductance becomes as high as 10(8). To overcome this problem we use Hybrid analysis and a variation of Conjugate Gradient method. Using this method we analyzed circuits containing resistors with large range of values, voltage sources and current sources and having size up to I million nodes and 3 million edges on 3GHZ pentium IV processor with 2GB RAM in less than 4 minutes. Also, we report the simulation timings for circuits containing diodes.
URI: http://dx.doi.org/10.1109/VLSI.Design.2009.27
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15605
http://hdl.handle.net/100/2074
ISBN: 978-0-7695-3506-7
ISSN: 1063-9667
Appears in Collections:Proceedings papers

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