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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/2071

Title: FPGA based high performance double-precision matrix multiplication
Authors: KUMAR, VBY
JOSHI, S
PATKAR, SB
NARAYANAN, H
Issue Date: 2009
Publisher: IEEE COMPUTER SOC
Citation: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS,341-346
Abstract: We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, an important kernel in many tile-based BLAS algorithms, optimized for implementation on high-end FPGAs. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from I to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for dcsign-I.
URI: http://dx.doi.org/10.1109/VLSI.Design.2009.13
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15603
http://hdl.handle.net/100/2071
ISBN: 978-0-7695-3506-7
ISSN: 1063-9667
Appears in Collections:Proceedings papers

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