A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection regime

Abstract

This paper analyzes in detail the correlation between gate and substrate currents in a deep sub-micron MOS transistor for different values of substrate voltage. The influence of channel length and oxide thickness on the gate injection and generation efficiency is studied from the point of non-volatile memories. The results show that the improvement of injection efficiency induced by the reverse substrate voltage becomes smaller as the gate length is reduced and also shows a turn around for smaller oxide thickness. The possible mechanisms responsible for such trends are discussed.