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|Title:||Development of a multi-FPGA netlist partitioner and a general purpose graph partitioning system|
|Publisher:||SPIE-INT SOC OPTICAL ENGINEERING|
|Citation:||PHOTOMASK AND X-RAY MASK TECHNOLOGY V,3412,252-260|
|Abstract:||We describe here a general purpose graph partitioning system, especially suitable for VLSI applications. The partitioner has at its core a spectral based graph partitioner. In our strategy, the input netlist is first coarsened into a smaller netlist and the core spectral partitioner then proceeds to partition this coarsened netlist. This coarse partition is then lifted to a partition of the original netlist. The coarsener is fairly subtle and uses the theory of submodular functions, and of matchings. We also highlight some of our results.|
|Appears in Collections:||Proceedings papers|
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