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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1914

Title: Channel engineering for sub-micron CMOS technologies
Authors: DIXIT, A
PAL, DK
ROY, JN
RAO, VR
Keywords: mosfet
Issue Date: 2002
Publisher: SPIE-INT SOC OPTICAL ENGINEERING
Citation: PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,637-640
Abstract: In this work, we have applied channel-engineering strategies for the Semiconductor Complex Limited (SCL) 0.8 mum CMOS process and studied the performance advantages using extensive 2-D device simulations. Our results clearly indicate that, with minimum adjustments to the process flow, one can achieve improved performance by appropriate choice of channel engineering techniques.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15251
http://hdl.handle.net/100/1914
ISBN: 0-8194-4500-2
ISSN: 0277-786X
Appears in Collections:Proceedings papers

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