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|Title:||Channel engineering for sub-micron CMOS technologies|
|Publisher:||SPIE-INT SOC OPTICAL ENGINEERING|
|Citation:||PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,637-640|
|Abstract:||In this work, we have applied channel-engineering strategies for the Semiconductor Complex Limited (SCL) 0.8 mum CMOS process and studied the performance advantages using extensive 2-D device simulations. Our results clearly indicate that, with minimum adjustments to the process flow, one can achieve improved performance by appropriate choice of channel engineering techniques.|
|Appears in Collections:||Proceedings papers|
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