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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1909

Title: High field stressing effects in JVD nitride capacitors
Authors: MANJULARANI, KN
RAO, VR
VASI, J
Keywords: border traps
interface
oxides
radiation
bias
Issue Date: 2002
Publisher: SPIE-INT SOC OPTICAL ENGINEERING
Citation: PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,1316-1319
Abstract: The performance of Jet Vapour Deposited (JVD) Silicon Nitride devices under high field stressing is reported in this paper. Border traps were generated when n-substrate capacitors were stressed with negative gate voltages. Also, an increase in bulk positive charges as well as interface trap density was observed. These results indicate that stressing under negative gate voltages may cause long term reliability problems in Metal-Nitride-Semiconductor (MNS) devices'. Stressing with positive gate voltage, however, does not show any significant degradation.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15250
http://hdl.handle.net/100/1909
ISBN: 0-8194-4500-2
ISSN: 0277-786X
Appears in Collections:Proceedings papers

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