DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1849

Title: Device scaling effects on substrate enhanced degradation in MOS transistors
Authors: MOHAPATRA, NR
MAHAPATRA, S
RAO, VR
Issue Date: 2002
Publisher: MATERIALS RESEARCH SOCIETY
Citation: SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY,716,287-292
Abstract: This paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15099
http://hdl.handle.net/100/1849
ISBN: 1-55899-652-4
ISSN: 0272-9172
Appears in Collections:Proceedings papers

Files in This Item:

There are no files associated with this item.

View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback