DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >
Please use this identifier to cite or link to this item:
|Title: ||Electrically induced junction MOSFET for high performance sub-50nm CMOS technology|
|Authors: ||DIXIT, A|
|Issue Date: ||2002|
|Publisher: ||MATERIALS RESEARCH SOCIETY|
|Citation: ||SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY,716,305-310|
|Abstract: ||Degrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.|
|Appears in Collections:||Proceedings papers|
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.