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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1767

Title: Dynamic threshold voltage MOSFETs for future low power sub 1V CMOS applications
Authors: SURYAGANDH, SS
ANAND, B
DESAI, MP
RAO, VR
Issue Date: 2000
Publisher: SPIE-INT SOC OPTICAL ENGINEERING
Citation: PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II,3975,655-658
Abstract: Threshold voltage scaling in deep sub-micron CMOS technologies is often dictated by the allowable off-state leakage currents and power dissipation. A recently proposed novel operation of a MOSFET is discussed in this paper, which is suitable for ultra low voltage operation (0.6 V or below) of ULSI circuits. In this mode of operation (referred to as Dynamic Threshold Voltage MOS, DTMOS), threshold voltage is made a function of gate voltage by tying the gate to the substrate of the MOSFET. Extensive comparisons are made in this work, using detailed device and circuit level simulations, on bulk DTMOS and conventional MOS structures. Our results show substantially higher drive currents and speeds for DTMOS operation, in comparison to the conventional MOSFET circuits, when the supply voltage is scaled below 1 V in the deep submicron technologies.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15226
http://hdl.handle.net/100/1767
ISBN: 0-8194-3601-1
ISSN: 0277-786X
Appears in Collections:Proceedings papers

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