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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1763

Title: Optimization and realization of sub 100nm channel length lateral asymmetric channel P-MOSFETS
Authors: HEMKAR, M
VASI, J
RAO, VR
CHENG, B
WOO, JCS
Issue Date: 2000
Publisher: SPIE-INT SOC OPTICAL ENGINEERING
Citation: PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II,3975,584-587
Abstract: Lateral Asymmetric Channel (LAC) p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated and characterized as part of this study. We show, for the first time, the results of extensive experiments done on LAC p-MOSFETs, including the effect of tilt angle of V-T adjust implant, on the device performance. Both uniform and asymmetric devices are fabricated on the same wafer for more accurate comparison.
URI: http://dspace.library.iitb.ac.in/xmlui/handle/10054/15225
http://hdl.handle.net/100/1763
ISBN: 0-8194-3601-1
ISSN: 0277-786X
Appears in Collections:Proceedings papers

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