Please use this identifier to cite or link to this item:
|Title:||Performance trade-offs by the use of high-K gate dielectrics in sub 100 nm channel length MOSFETs|
|Publisher:||SPIE-INT SOC OPTICAL ENGINEERING|
|Citation:||PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II,3975,896-899|
|Abstract:||High-k gate dielectrics are currently under extensive investigation, for use in sub quarter micron MOSFETs, to suppress the gate leakage current. However, the performance degradation because of the increased fringing field effects, due to the higher physical thickness of a high-K dielectric in relation to the channel length, has attracted considerable attention. Tn this work, we show a way to confine the fringing field effects in a sub 100nm channel Length MOSFET by using a low-K material as a spacer dielectric. We present extensive device simulations on a 70 nm channel length MOSFET with different high-k gate and low-K spacer materials, and analyze the resulting performance issues.|
|Appears in Collections:||Proceedings papers|
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.