Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/100/15732
Title: Silicon Tunneling Field-Effect Transistors With Tunneling in Line With the Gate Field
Authors: FISCHER, IA
BAKIBILLAH, ASM
GOLVE, M
HAHNEL, D
ISEMANN, H
KOTTANTHARAYIL, A
OEHME, M
SCHULZE, J
Keywords: Semiconductor Devices
Transistors
Tunneling
Tunneling Field-Effect Transistor (Tfet)
Issue Date: 2013
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE ELECTRON DEVICE LETTERS, 34(2)154-156
Abstract: We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with I-ON = 1.1 mu A/mu m at V-DS = 0.5 V and an I-ON/I-OFF ratio of 3.4.10(4) in n-channel operation. We present further suggestions for device improvements.
URI: http://dx.doi.org/10.1109/LED.2012.2228250
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