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|Title:||Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx|
Equivalent Oxide Thickness (Eot) Scaling
Interlayer (Il) Scaling
Negative-Bias Temperature Instability (Nbti)
Positive-Bias Temperature Instability (Pbti)
|Publisher:||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC|
|Citation:||IEEE ELECTRON DEVICE LETTERS, 34(1)3-5|
|Abstract:||The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to similar to 6 angstrom, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.|
|Appears in Collections:||Article|
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