Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/100/15540
Title: Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx
Authors: JOSHI, K
HUNG, S
MUKHOPADHYAY, S
SATO, T
BEVAN, M
RAJAMOHANAN, B
WEI, A
NOORI, A
MCDOUGALL, B
NI, C
LAZIK, C
SAHELI, G
LIU, P
CHU, D
DATE, L
DATTA, S
BRAND, A
SWENBERG, J
MAHAPATRA, S
Keywords: Dciv
Equivalent Oxide Thickness (Eot) Scaling
Flicker Noise
Gate Leakage
Hkmg
Interlayer (Il) Scaling
Mobility
Negative-Bias Temperature Instability (Nbti)
Positive-Bias Temperature Instability (Pbti)
Issue Date: 2013
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE ELECTRON DEVICE LETTERS, 34(1)3-5
Abstract: The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to similar to 6 angstrom, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.
URI: http://dx.doi.org/10.1109/LED.2012.2222338
http://dspace.library.iitb.ac.in/jspui/handle/100/15540
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