DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/100/1413

Title: Sub-100 nm CMOS circuit performance with high-K gate dielectrics
Authors: MOHAPATRA, NR
DUTTA, A
SRIDHAR, G
DESAI, MP
RAO, VR
Keywords: mosfets
Issue Date: 2001
Publisher: PERGAMON-ELSEVIER SCIENCE LTD
Citation: MICROELECTRONICS RELIABILITY,41(7)1045-1048
Abstract: In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO2 is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance. (C) 2001 Elsevier Science Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/S0026-2714(01)00068-3
http://dspace.library.iitb.ac.in/xmlui/handle/10054/14589
http://hdl.handle.net/100/1413
ISSN: 0026-2714
Appears in Collections:Proceedings papers

Files in This Item:

There are no files associated with this item.

View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback