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|Title: ||Sub-100 nm CMOS circuit performance with high-K gate dielectrics|
|Authors: ||MOHAPATRA, NR|
|Issue Date: ||2001|
|Publisher: ||PERGAMON-ELSEVIER SCIENCE LTD|
|Citation: ||MICROELECTRONICS RELIABILITY,41(7)1045-1048|
|Abstract: ||In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO2 is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance. (C) 2001 Elsevier Science Ltd. All rights reserved.|
|Appears in Collections:||Proceedings papers|
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