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Browsing by Author SHARMA, DK

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Issue DateTitleAuthor(s)
2009Benchmarking the device performance at SUB 22 NM node technologies using an SOC frameworkSHRIVASTAVA, M; VERMA, B; BAGHINI, MS; RUSS, C; SHARMA, DK; GOSSNER, H; RAO, VR
1997Charge trapping behaviour in deposited and grown thin metal-oxide-semiconductor gate dielectricsRAO, VR; HANSCH, W; BAUMGARTNER, H; EISELE, I; SHARMA, DK; VASI, J; GRABOLLA, T
2002Determination of semiconductor resistance under a contactAHMAD, M; SHAH, AP; SHARMA, DK; ROY, NR; ARORA, BM
1998Device simulation for radiation and hot carrier effectsSHARMA, DK; EKBOTE, S; ZAMAN, P; SUBBARAMAN, S; DAS, A; VASI, J
2004Evaluation of pausible clocking for interfacing high speed IP cores in GALS frameworkMEKIE, JOYCEE; CHAKRABORTY, SUPRATIK; SHARMA, DK
2005Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETsPATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V
2005Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETsKUMAR, DV; NARASIMHULU, K; REDDY, PS; SHOJAEI-BAGHINI, M; SHARMA, DK; PATIL, MB; RAO, VR
1990Gallium arsenide photo-MESFET'sLAKSHMI, B; CHALAPATI, K; SRIVASTAVA, AK; ARORA, BM; SUBRAMANIAN, S; SHARMA, DK
2008Gate fringe-induced barrier lowering in underlap FinFET structures and its optimizationSACHID, AB; MANOJ, CR; SHARMA, DK; RAO, VR
1997High-field stressing of LPCVD gate oxidesRAMGOPAL RAO, V; EISELE, I; PATRIKAR, RM; SHARMA, DK; GRABOLLA, T; VASI, J
2009Highly robust nanoscale planar double-Gate MOSFET Device and SRAM cell immune to Gate-misalignment and process variationsSACHID, AB; KULKARNI, GS; BAGHINI, MS; SHARMA, DK; RAO, VR
1998HOTMOS : a 2-D MOS device simulator for hot carrier effectsSUBBARAMAN, S; SHARMA, DK; VASI, J; DAS, A
2003Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performanceSHARMA, DK; NARASIMHULU, K; RAMGOPAL RAO, V
2006Interface design for rationally clocked GALS systemsMEKIE, JOYCEE; CHAKRABORTY, SUPRATIK; VENKATARAMANI, G; THIAGARAJAN, PS; SHARMA, DK
2005A low-power and compact analog CMOS processing chip for portable ECG recordersBAGHINI, MS; LAL, RAKESH; SHARMA, DK
1999Low temperature-high pressure grown thin gate dielectrics for MOS applicationsRAMGOPAL RAO, V; MAHAPATRA, S; SHARMA, DK; VASI, J; GRABOLLA, T; EISELE, I; HANSCH, W
2004Macroporous silicon based capacitive affinity sensor-fabrication and electrochemical studiesBETTY, CA; LAL, R; SHARMA, DK; YAKHMI, JV; MITTAL, JP
2002MEMS: technology, design, CAD and applicationsLAL, RAKESH; APTE, PR; BHAT, KN; BOSE, G; CHANDRA, S; SHARMA, DK
1998A Monte Carlo approach for incorporation of memory effect in switched gate bias experimentsSUBBARAMAN, S; SHARMA, DK; VASI, J; DAS, A
2005NBTI degradation and its impact for analog circuit reliabilityRAMGOPAL RAO, V; JHA, NEERAJ K; REDDY, PS; SHARMA, DK
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