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DSpace at IIT Bombay >
Browsing by Author SHARMA, DK
Showing results 1 to 20 of 40
| Issue Date | Title | Author(s) | | 2009 | Benchmarking the device performance at SUB 22 NM node technologies using an SOC framework | SHRIVASTAVA, M; VERMA, B; BAGHINI, MS; RUSS, C; SHARMA, DK; GOSSNER, H; RAO, VR |
| 1997 | Charge trapping behaviour in deposited and grown thin metal-oxide-semiconductor gate dielectrics | RAO, VR; HANSCH, W; BAUMGARTNER, H; EISELE, I; SHARMA, DK; VASI, J; GRABOLLA, T |
| 2002 | Determination of semiconductor resistance under a contact | AHMAD, M; SHAH, AP; SHARMA, DK; ROY, NR; ARORA, BM |
| 1998 | Device simulation for radiation and hot carrier effects | SHARMA, DK; EKBOTE, S; ZAMAN, P; SUBBARAMAN, S; DAS, A; VASI, J |
| 2004 | Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework | MEKIE, JOYCEE; CHAKRABORTY, SUPRATIK; SHARMA, DK |
| 2005 | Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs | PATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V |
| 2005 | Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs | KUMAR, DV; NARASIMHULU, K; REDDY, PS; SHOJAEI-BAGHINI, M; SHARMA, DK; PATIL, MB; RAO, VR |
| 1990 | Gallium arsenide photo-MESFET's | LAKSHMI, B; CHALAPATI, K; SRIVASTAVA, AK; ARORA, BM; SUBRAMANIAN, S; SHARMA, DK |
| 2008 | Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization | SACHID, AB; MANOJ, CR; SHARMA, DK; RAO, VR |
| 1997 | High-field stressing of LPCVD gate oxides | RAMGOPAL RAO, V; EISELE, I; PATRIKAR, RM; SHARMA, DK; GRABOLLA, T; VASI, J |
| 2009 | Highly robust nanoscale planar double-Gate MOSFET Device and SRAM cell immune to Gate-misalignment and process variations | SACHID, AB; KULKARNI, GS; BAGHINI, MS; SHARMA, DK; RAO, VR |
| 1998 | HOTMOS : a 2-D MOS device simulator for hot carrier effects | SUBBARAMAN, S; SHARMA, DK; VASI, J; DAS, A |
| 2003 | Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance | SHARMA, DK; NARASIMHULU, K; RAMGOPAL RAO, V |
| 2006 | Interface design for rationally clocked GALS systems | MEKIE, JOYCEE; CHAKRABORTY, SUPRATIK; VENKATARAMANI, G; THIAGARAJAN, PS; SHARMA, DK |
| 2005 | A low-power and compact analog CMOS processing chip for portable ECG recorders | BAGHINI, MS; LAL, RAKESH; SHARMA, DK |
| 1999 | Low temperature-high pressure grown thin gate dielectrics for MOS applications | RAMGOPAL RAO, V; MAHAPATRA, S; SHARMA, DK; VASI, J; GRABOLLA, T; EISELE, I; HANSCH, W |
| 2004 | Macroporous silicon based capacitive affinity sensor-fabrication and electrochemical studies | BETTY, CA; LAL, R; SHARMA, DK; YAKHMI, JV; MITTAL, JP |
| 2002 | MEMS: technology, design, CAD and applications | LAL, RAKESH; APTE, PR; BHAT, KN; BOSE, G; CHANDRA, S; SHARMA, DK |
| 1998 | A Monte Carlo approach for incorporation of memory effect in switched gate bias experiments | SUBBARAMAN, S; SHARMA, DK; VASI, J; DAS, A |
| 2005 | NBTI degradation and its impact for analog circuit reliability | RAMGOPAL RAO, V; JHA, NEERAJ K; REDDY, PS; SHARMA, DK |
Showing results 1 to 20 of 40
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