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Browsing by Author SATO, T

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Issue DateTitleAuthor(s)
2013Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOxJOSHI, K; HUNG, S; MUKHOPADHYAY, S; SATO, T; BEVAN, M; RAJAMOHANAN, B; WEI, A; NOORI, A; MCDOUGALL, B; NI, C; LAZIK, C; SAHELI, G; LIU, P; CHU, D; DATE, L; DATTA, S; BRAND, A; SWENBERG, J; MAHAPATRA, S
2002Size and orientation of the fault plane for the 2001 Gujarat, India earthquake (Mw7.7) from aftershock observations: A high stress drop eventNEGISHI, H; MORI, J; SATO, T; SINGH, R; KUMAR, S; HIRATA, N
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