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Browsing by Author SATHE, C

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Issue Date	Title	Author(s)
2008	Assessment of SET logic robustness through noise margin modeling	SATHE, C; DAN, SS; MAHAPATRA, S
2009	Automated design and optimization of circuits in emerging technologies	THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2009	A Novel Table-Based Approach for Design of FinFET Circuits	THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2010	A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance	THAKKER, RA; SATHE, C; BAGHINI, MS; PATIL, MB

Showing results 1 to 4 of 4