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Browsing by Author SATHE, C

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Issue DateTitleAuthor(s)
2008Assessment of SET logic robustness through noise margin modelingSATHE, C; DAN, SS; MAHAPATRA, S
2009Automated design and optimization of circuits in emerging technologiesTHAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2009A Novel Table-Based Approach for Design of FinFET CircuitsTHAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2010A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit PerformanceTHAKKER, RA; SATHE, C; BAGHINI, MS; PATIL, MB
Showing results 1 to 4 of 4

 

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