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DSpace at IIT Bombay >
Browsing by Author SACHID, AB
Showing results 1 to 8 of 8
| Issue Date | Title | Author(s) | | 2009 | Automated design and optimization of circuits in emerging technologies | THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB |
| 2009 | Drain current model for nanoscale double-gate MOSFETs | HARIHARAN, V; THAKKER, R; SINGH, K; SACHID, AB; PATIL, MB; VASI, J; RAO, VR |
| 2008 | Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization | SACHID, AB; MANOJ, CR; SHARMA, DK; RAO, VR |
| 2009 | Highly robust nanoscale planar double-Gate MOSFET Device and SRAM cell immune to Gate-misalignment and process variations | SACHID, AB; KULKARNI, GS; BAGHINI, MS; SHARMA, DK; RAO, VR |
| 2010 | Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs | MANOJ, CR; SACHID, AB; YUAN, F; CHANG, CY; RAO, VR |
| 2008 | A Novel and robust approach for common mode feedback using IDDG FinFET | SHRIVASTAVA, MAYANK; BAGHINI, MS; SACHID, AB; SHARMA, DK; RAMGOPAL RAO, V |
| 2009 | A Novel Table-Based Approach for Design of FinFET Circuits | THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB |
| 2008 | Sub-20 nm gate length FinFET design : can High-kappa spacers make a difference? | SACHID, AB; FRANCIS, R; BAGHINI, MS; SHARMA, DK; BACH, KH; MAHNKOPF, R; RAO, VR |
Showing results 1 to 8 of 8
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