Browsing by Author RAO, VR

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Issue DateTitleAuthor(s)
20091/f Noise in Drain and Gate Current of MOSFETs With High-k Gate StacksMAGNONE, P; CRUPI, F; GIUSI, G; PACE, C; SIMOEN, E; CLAEYS, C; PANTISANO, L; MAJI, D; RAO, VR; SRINIVASAN, P
2007Affinity cantilever sensors for cardiac diagnosticsJOSHI, M; KALE, N; MUKHERJI, S; LAL, R; RAO, VR
2013Al-doped ZnO thin-film transistor embedded micro-cantilever as a piezoresistive sensorRAY, P; RAO, VR
1998Alumina addition to fluoride slags for recycling of low oxygen high conductivity copper scrap through electroslag crucible meltingPRASAD, VVS; RAO, AS; PRAKASH, U; RAO, VR; RAO, PK; GUPT, KM
2006Analog device and circuit performance degradation under substrate bias enhanced hot carrier stressNARASIMHULU, K; RAO, VR
2010Analysis of Threshold Voltage Variation in Fin Field Effect Transistors: Separation of Short Channel EffectsKOBAYASHI, Y; TSUTSUI, K; KAKUSHIMA, K; AHMET, P; RAO, VR; IWAI, H
2016Anomalous diffusion mediated kinetic modelling of surface-stress sensorsKUSHAGRA, A; RAO, VR
2015Anomalous Width Dependence of Gate Current in High-K Metal Gate nMOS TransistorsDUHAN, P; GANERIWALA, MD; RAO, VR; MOHAPATRA, NR
2016Asymmetric immobilization of antibodies on a piezo-resistive micro-cantilever surfaceAGARWAL, DK; MAHESHWARI, N; MUKHERJI, S; RAO, VR
2009Automated design and optimization of circuits in emerging technologiesTHAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2009Benchmarking the device performance at SUB 22 NM node technologies using an SOC frameworkSHRIVASTAVA, M; VERMA, B; BAGHINI, MS; RUSS, C; SHARMA, DK; GOSSNER, H; RAO, VR
2009Bio-functionalization of silicon nitride-based piezo-resistive microcantileversKALE, NS; JOSHI, M; RAO, PN; MUKHERJI, S; RAO, VR
2009A CAD-compatible closed form approximation for the inversion charge areal density in double-gate MOSFETsHARIHARAN, V; VASI, J; RAO, VR
2002Channel engineering for sub-micron CMOS technologiesDIXIT, A; PAL, DK; ROY, JN; RAO, VR
2002Characterization and simulation of lateral asymmetric channel silicon-on-insulator MOSFETsNAJEEB-UD-DIN; RAO, VR; VASI, J
2009Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV techniqueMAJI, D; CRUPI, F; MAGNONE, P; GIUSI, G; PACE, C; SIMOEN, E; RAO, VR
1997Charge trapping behaviour in deposited and grown thin metal-oxide-semiconductor gate dielectricsRAO, VR; HANSCH, W; BAUMGARTNER, H; EISELE, I; SHARMA, DK; VASI, J; GRABOLLA, T
2009Chemical vapor deposition precursors for high dielectric oxides: zirconium and hafnium oxideWALAWALKAR, MG; KOTTANTHARAYIL, A; RAO, VR
2003CHISEL programming operation of scaled NOR flash EEPROMs - Effect of voltage scaling, device scaling and technological parametersMOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAO, VR; SHUKURI, S; BUDE, JD
2007Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasiticsANAND, B; RAO, VR; DESAI, MP