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Issue DateTitleAuthor(s)
200920GHz CMOS distributed voltage controlled oscillators with frequency tuning by MOS varactorsBHATTACHARYYA, K; MUKHERJEE, J; BAGHINI, MS
200927.1GHz CMOS distributed voltage controlled oscillators with body bias for frequency tuning of 1.28GHzBHATTACHARYYA, K; MUKHERJEE, J; BAGHINI, MS
20106-bit low-power subranging-ADC with increased throughputGOWDHAMAN, SK; BAGHINI, MS
2009Automated design and optimization of circuits in emerging technologiesTHAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2009Benchmarking the device performance at SUB 22 NM node technologies using an SOC frameworkSHRIVASTAVA, M; VERMA, B; BAGHINI, MS; RUSS, C; SHARMA, DK; GOSSNER, H; RAO, VR
2010Comments on "An Analog 2-D DCT Processor"NOOLU, SP; BAGHINI, MS
2010Comments on "Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing"KARANJKAR, NV; SAHOO, RR; BAGHINI, MS
2009DC & transient circuit simulation methodologies for organic electronicsNAVAN, RR; THAKKER, RA; TIWARI, SP; BAGHINI, MS; PATIL, MB; MHAISALKAR, SG; RAO, VR
2005Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETsPATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V
2009Filament study of sti type drain extended nmos device using transient interferometric mappingSHRIVASTAVA, M; BYCHIKHIN, S; POGANY, D; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; GORNIK, E; RAO, VR
2009A generic analytical model of switching characteristics for efficiency-oriented design and optimization of CMOS integrated buck convertersMODAK, R; BAGHINI, MS
2009Highly resistive body STI Ndemos : an optimized demos device to achieve moving current filaments for robust ESD protectionSHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR
2009Highly robust nanoscale planar double-Gate MOSFET Device and SRAM cell immune to Gate-misalignment and process variationsSACHID, AB; KULKARNI, GS; BAGHINI, MS; SHARMA, DK; RAO, VR
2002Impact of technology scaling on metastability performance of CMOS synchronizing latchesBAGHINI, MS; DESAI, MP
2005A low-power and compact analog CMOS processing chip for portable ECG recordersBAGHINI, MS; LAL, RAKESH; SHARMA, DK
2009Low-power low-voltage analog circuit design using hierarchical particle swarm optimizationTHAKKER, RA; BAGHINI, MS; PATIL, MB
2007Microstrip equivalent parasitics modeling of RFIC interconnectsMUKHERJEE, JAYANTA; YOUNG-GI KIM; INWON SUH; ROBLIN, PATRICK; YAO-CHIAN LIN; WAN RONE LIOU; BAGHINI, MS
2009A new physical insight and 3D device modeling of sti type denmos device failure under ESD conditionsSHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR
2008A Novel and robust approach for common mode feedback using IDDG FinFETSHRIVASTAVA, MAYANK; BAGHINI, MS; SACHID, AB; SHARMA, DK; RAMGOPAL RAO, V
2011A novel architecture for improving slew rate in FinFET-based op-amps and OTAsTHAKKER, RA; SRIVASTAVA, M; TAILOR, KH; BAGHINI, MS; SHARMA, DK; RAO, VR; PATIL, MB
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