Browsing by Author RAO, VR

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Issue DateTitleAuthor(s)
2015Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate All Around Nanowire n-MOSFETNAYAK, K; AGARWAL, S; BAJAJ, M; MURALI, KVRM; RAO, VR
2007Rare earth oxides in microelectronicsKAKUSHIMA, K; TSUTSUI, K; OHMI, SI; AHMET, P; RAO, VR; IWAI, H
1996Recycling of superalloy scrap through electro slag remeltingPRASAD, VVS; RAO, AS; PRAKASH, U; RAO, VR; RAO, PK; GUPT, KM
2002Recycling of valuable scrap through electroslag processingPRASAD, VVS; RAO, AS; PRAKASH, U; RAO, VR; RAO, PK; GUPT, KM
2002Reliability issues of ultra thin silicon nitride (a-SiN : H) by hot wire CVD for deep sub-micron CMOS technologiesWAGHMARE, PC; PATIL, SB; KUMBHAR, A; DUSANE, RO; RAO, VR
2014Role of Injection Barrier in Capacitance-Voltage Measurements of Organic DevicesNIGAM, A; NAIR, PR; PREMARATNE, M; RAO, VR
2015Sensing of Stimulus Artifact Suppressed Signals From Electrode InterfacesNAG, S; SIKDAR, SK; THAKOR, NV; RAO, VR; SHARMA, D
2001A simple and direct technique for interface characterization of SOI MOSFETs and its application in hot carrier degradation studies in sub-100 nm JVD MNSFETsKUMAR, A; LAL, R; RAO, VR
2012Solution processed photopatternable high-k nanocomposite gate dielectric for low voltage organic field effect transistorsNAVAN, RR; PRASHANTHI, K; BAGHINI, MS; RAO, VR
2010A Solution Toward the OFF-State Degradation in Drain-Extended MOS DeviceSHRIVASTAVA, M; JAIN, R; BAGHINI, MS; GOSSNER, H; RAO, VR
2009Solution-Processed Bootstrapped Organic Inverters Based on P3HT With a High-k Gate Dielectric MaterialRAVAL, HN; TIWARI, SP; NAVAN, RR; MHAISALKAR, SG; RAO, VR
2015Spin-coatable, photopatternable magnetic nanocomposite thin films for MEMS device applicationsKANDPAL, M; SHARAN, C; PALAPARTHY, V; TIWARY, N; PODDAR, P; RAO, VR
2002Status and trends in molecular electronicsRASTOGI, S; RAO, VR; JHAVERI, R; MUKHERJI, S; RAVIKANTH, M
2012Strain induced anisotropic effect on electron mobility in C-60 based organic field effect transistorsNIGAM, A; SCHWABEGGER, G; ULLAH, M; AHMED, R; FISHCHUK, II; KADASHCHUK, A; SIMBRUNNER, C; SITTER, H; PREMARATNE, M; RAO, VR
1999A study of 100 nm channel length asymmetric channel MOSFET by using charge pumpingMAHAPATRA, S; RAO, VR; PARIKH, CD; VASI, J; CHENG, B; WOO, JCS
2001A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping techniqueMAHAPATRA, S; RAO, VR; VASI, J; CHENG, B; WOO, JCS
2013Sub 0.5 V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET DevicesRAJORIYA, A; SHRIVASTAVA, M; GOSSNER, H; SCHULZ, T; RAO, VR
2001Sub-100 nm CMOS circuit performance with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; SRIDHAR, G; DESAI, MP; RAO, VR
2008Sub-20 nm gate length FinFET design : can High-kappa spacers make a difference?SACHID, AB; FRANCIS, R; BAGHINI, MS; SHARMA, DK; BACH, KH; MAHNKOPF, R; RAO, VR