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Browsing by Author RAO, VR

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Issue DateTitleAuthor(s)
2014Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuitsNAYAK, K; BAJAJ, M; KONAR, A; OLDIGES, PJ; IWAI, H; MURALI, KVRM; RAO, VR
1996Neutral electron trap generation under irradiation in reoxidized nitrided gate dielectricsRAO, VR; SHARMA, DK; VASI, J
2005A new oxide trap-assisted NBTI degradation modelJHA, NK; RAO, VR
2009A new physical insight and 3D device modeling of sti type denmos device failure under ESD conditionsSHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR
2011A novel architecture for improving slew rate in FinFET-based op-amps and OTAsTHAKKER, RA; SRIVASTAVA, M; TAILOR, KH; BAGHINI, MS; SHARMA, DK; RAO, VR; PATIL, MB
2010A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal PerformanceSHRIVASTAVA, M; BAGHINI, MS; SHARMA, DK; RAO, VR
2012A Novel Drain-Extended FinFET Device for High-Voltage High-Speed ApplicationsSHRIVASTAVA, M; GOSSNER, H; RAO, VR
2012A Novel Photoplastic Piezoelectric Nanocomposite for MEMS ApplicationsPRASHANTHI, K; NARESH, M; SEENA, V; THUNDAT, T; RAO, VR
2009A Novel Table-Based Approach for Design of FinFET CircuitsTHAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB
2008On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN/TaN/HfO(2)/SiO(2) gate stackMAJI, D; CRUPI, F; GIUSI, G; PACE, C; SIMOEN, E; CLAEYS, C; RAO, VR
2010On the differences between 3D filamentation and failure of N & P type drain extended MOS devices under ESD conditionSHRIVASTAVA, M; BYCHIKHIN, S; POGANY, D; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; GORNIK, E; RAO, VR
2010On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditionsSHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR
2000Optimization and realization of sub 100nm channel length lateral asymmetric channel P-MOSFETSHEMKAR, M; VASI, J; RAO, VR; CHENG, B; WOO, JCS
2014Optimization of a plasma immersion ion implantation process for shallow junctions in siliconRAY, A; NORI, R; BHATT, P; LODHA, S; PINTO, R; RAO, VR; JOMARD, F; NEUMANN-SPALLART, M
2014Optimization of a plasma immersion ion implantation process for shallow junctions in siliconRAY, A; NORI, R; BHATT, P; LODHA, S; PINTO, R; RAO, VR; JOMARD, F; NEUMANN-SPALLART, M
2002Optimization of sub 100 nm gamma-gate Si-MOSFETs for RF applicationsGUPTA, M; VIDYA, V; RAO, VR; TO, KH; WOO, JCS
2009Optimum Body Bias Constraints for Leakage Reduction in High-k Complementary Metal-Oxide-Semiconductor CircuitsCHAWDA, PK; ANAND, B; RAO, VR
2012Organic CantiFET: A Nanomechanical Polymer Cantilever Sensor With Integrated OFETSEENA, V; NIGAM, A; PANT, P; MUKHERJI, S; RAO, VR
2008Organic FETs with HWCVD silicon nitride as a passivation layer and gate dielectricTIWARI, SP; SNINIVAS, P; SHRIRAM, S; KALE, NS; MHAISALKAR, SG; RAO, VR
2007Parasitic effects in multi-gate MOSFETsKOBAYASHI, Y; MANOJ, CR; TSUTSUI, K; HARIHARAN, V; KAKUSHIMA, K; RAO, VR; AHMET, P; IWAI, H
Showing results 92 to 111 of 161
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