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DSpace at IIT Bombay >
Browsing by Author RAO, VR
Showing results 69 to 88 of 119
| Issue Date | Title | Author(s) | | 2003 | Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2001 | Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETs | KUMAR, A; MAHAPATRA, S; LAL, R; RAO, VR |
| 1996 | Neutral electron trap generation under irradiation in reoxidized nitrided gate dielectrics | RAO, VR; SHARMA, DK; VASI, J |
| 2005 | A new oxide trap-assisted NBTI degradation model | JHA, NK; RAO, VR |
| 2009 | A new physical insight and 3D device modeling of sti type denmos device failure under ESD conditions | SHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR |
| 2011 | A novel architecture for improving slew rate in FinFET-based op-amps and OTAs | THAKKER, RA; SRIVASTAVA, M; TAILOR, KH; BAGHINI, MS; SHARMA, DK; RAO, VR; PATIL, MB |
| 2010 | A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance | SHRIVASTAVA, M; BAGHINI, MS; SHARMA, DK; RAO, VR |
| 2009 | A Novel Table-Based Approach for Design of FinFET Circuits | THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB |
| 2008 | On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN/TaN/HfO(2)/SiO(2) gate stack | MAJI, D; CRUPI, F; GIUSI, G; PACE, C; SIMOEN, E; CLAEYS, C; RAO, VR |
| 2010 | On the differences between 3D filamentation and failure of N & P type drain extended MOS devices under ESD condition | SHRIVASTAVA, M; BYCHIKHIN, S; POGANY, D; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; GORNIK, E; RAO, VR |
| 2010 | On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions | SHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR |
| 2000 | Optimization and realization of sub 100nm channel length lateral asymmetric channel P-MOSFETS | HEMKAR, M; VASI, J; RAO, VR; CHENG, B; WOO, JCS |
| 2002 | Optimization of sub 100 nm gamma-gate Si-MOSFETs for RF applications | GUPTA, M; VIDYA, V; RAO, VR; TO, KH; WOO, JCS |
| 2009 | Optimum Body Bias Constraints for Leakage Reduction in High-k Complementary Metal-Oxide-Semiconductor Circuits | CHAWDA, PK; ANAND, B; RAO, VR |
| 2008 | Organic FETs with HWCVD silicon nitride as a passivation layer and gate dielectric | TIWARI, SP; SNINIVAS, P; SHRIRAM, S; KALE, NS; MHAISALKAR, SG; RAO, VR |
| 2007 | Parasitic effects in multi-gate MOSFETs | KOBAYASHI, Y; MANOJ, CR; TSUTSUI, K; HARIHARAN, V; KAKUSHIMA, K; RAO, VR; AHMET, P; IWAI, H |
| 2006 | Parasitics effects in multi gate MOSFETs | MANOJ, CR; MANGAL, A; RAO, VR; TSUTSUI, K; IWAI, H |
| 2010 | Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices | SHRIVASTAVA, M; BAGHINI, MS; GOSSNER, H; RAO, VR |
| 2010 | Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions | SHRIVASTAVA, M; GOSSNER, H; BAGHINI, MS; RAO, VR |
| 2010 | Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices | SHRIVASTAVA, M; BAGHINI, MS; GOSSNER, H; RAO, VR |
Showing results 69 to 88 of 119
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