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DSpace at IIT Bombay >
Browsing by Author RAO, VR
Showing results 57 to 76 of 119
| Issue Date | Title | Author(s) | | 2010 | Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs | MANOJ, CR; SACHID, AB; YUAN, F; CHANG, CY; RAO, VR |
| 2007 | Impact of halo doping on the subthreshold performance of deep-submicrometer CMOS devices and circuits for ultralow power analog/mixed-signal applications | CHAKRABORTY, S; MALLIK, A; SARKAR, CK; RAO, VR |
| 2007 | Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs | MANOJ, CR; RAO, VR |
| 2010 | Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs | CHABUKSWAR, S; MAJI, D; MANOJ, CR; ANIL, KG; RAO, VR; CRUPI, F; MAGNONE, P; GIUSI, G; PACE, C; COLLAERT, N |
| 2002 | Improvement in gate dielectric quality of ultra thin a : SiN : H MNS capacitor by hydrogen etching of the substrate | WAGHMARE, PC; PATIL, SB; DUSANE, RO; RAO, VR |
| 2009 | An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs | HARIHARAN, V; VASI, J; RAO, VR |
| 2007 | Improving the DC performance of bulk FinFETs by optimum body doping | MANOJ, CR; NAGPAL, M; RAO, VR |
| 2007 | Investigations of enhanced device characteristics in pentacene-based field effect transistors with sol-gel interfacial layer | CAHYADI, T; TEY, JN; MHAISALKAR, SG; BOEY, F; RAO, VR; LAL, R; HUANG, ZH; QI, GJ; CHEN, ZK; NG, CM |
| 2010 | Low-Operating-Voltage Operation and Improvement in Sensitivity With Passivated OFET Sensors for Determining Total Dose Radiation | RAVAL, HN; RAO, VR |
| 2000 | Low temperature hot-wire CVD nitrides for deep sub-micron CMOS technologies | PATIL, SB; VAIDYA, S; KUMBHAR, A; DUSANE, RO; CHANDORKAR, AN; RAO, VR |
| 2001 | Low temperature silicon nitride deposited by Cat-CVD for deep submicron metal-oxide-semiconductor devices | PATIL, SB; KUMBHAR, A; WAGHMARE, P; RAO, VR; DUSANE, RO |
| 2002 | Microcantilever based biosensors | PORWAL, A; NARSUDE, M; RAO, VR; MUKHERJI, S |
| 2003 | Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2001 | Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETs | KUMAR, A; MAHAPATRA, S; LAL, R; RAO, VR |
| 1996 | Neutral electron trap generation under irradiation in reoxidized nitrided gate dielectrics | RAO, VR; SHARMA, DK; VASI, J |
| 2005 | A new oxide trap-assisted NBTI degradation model | JHA, NK; RAO, VR |
| 2009 | A new physical insight and 3D device modeling of sti type denmos device failure under ESD conditions | SHRIVASTAVA, M; SCHNEIDER, J; BAGHINI, MS; GOSSNER, H; RAO, VR |
| 2011 | A novel architecture for improving slew rate in FinFET-based op-amps and OTAs | THAKKER, RA; SRIVASTAVA, M; TAILOR, KH; BAGHINI, MS; SHARMA, DK; RAO, VR; PATIL, MB |
| 2010 | A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance | SHRIVASTAVA, M; BAGHINI, MS; SHARMA, DK; RAO, VR |
| 2009 | A Novel Table-Based Approach for Design of FinFET Circuits | THAKKER, RA; SATHE, C; SACHID, AB; BAGHINI, MS; RAO, VR; PATIL, MB |
Showing results 57 to 76 of 119
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